1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a non-volatile memory and a manufacturing method thereof.
2. Description of Related Art
Since operations such as data programming, reading, and erasing to non-volatile memories for multiple times, and the non-volatile memories have the advantage that data stored therein do not disappear after the power is turned off, the non-volatile memories have been broadly used in personal computer and electronic apparatuses.
The conventional non-volatile memory is designed to have a stack gate structure including a tunneling oxidation layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially disposed on a substrate. When pertaining a programming or erasing operation to the flash memory device, appropriate voltages are respectively applied to a source region, a drain region, and the control gate, such that electrons are injected into a polysilicon floating gate or pulled out from the polysilicon floating gate.
Usually, in an operation of the non-volatile memory, if a gate-coupling ratio (GCR) between the floating gate and the control gate is greater, an operational voltage required becomes lower, and an operational speed and efficiency of the flash memory thus increase significantly. The GCR may be increased by increasing an overlapped area between the floating gate and the control gate, decreasing a thickness of a dielectric layer between the floating gate and the control gate, and increasing a dielectric constant (i.e., k) of an inter-gate dielectric layer between the floating gate and the control gate, etc.
However, as integrated circuits are developed toward a miniaturized device with a higher integrity, the size of memory cells of the non-volatile memories needs to be reduced to increase the integrity. The size of memory cells may be reduced by reducing a gate length of the memory cell and separation of bit lines. However, reducing the gate length also reduces the length of a channel below the tunneling oxidation layer, which may easily induce an undesired electrical punch through between the drain region and the source region and consequently influence the performance of the memory cell. Besides, when programming or erasing the memory cells, the electrons may repetitively pass through the tunneling oxidation layer, resulting in the decreasing of quality of the tunneling oxidation layer and consequently reducing the reliability of the memory device.